Proceedings of the 23rd Int'l Conference on Supercomputing (ICS), pp. 56~67, IBM T. J. Watson Research Center, NY, June 2009.
This paper proposes DCC (Dynamic Cache Clustering), a novel distributed cache management scheme for large-scale chip multiprocessors. Using DCC, a per-core cache cluster is comprised of a number of L2 cache banks and cache clusters are constructed, expanded, and contracted dynamically to match each core's cache demand. The basic tradeoffs of varying the on-chip cache clusters are Average L2 Access Latency (AAL) and L2 Miss Rate (MR). DCC uniquely and efficiently optimizes both the metrics and continuously tracks a near-optimal cache organization from many possible configurations. Simulation results using a full-system simulator demonstrate that DCC outperforms alternative L2 cache designs.