IEEE Transactions on Semiconductor Manufacturing (TSM), 21(1):55~62, February 2008.
Process-induced variability has become a predominant limiter of performance and yield of IC products especially in a deep sub-micron technology. However, it is difficult to accurately model systematic process variability due to the complicated and inter-related nature of physical mechanisms of variation. We present a simple and practical method to decompose process variability using statistics of the measurements from manufacturing in-line test structures without assuming any underlying model for process variation. The decomposition method utilizes a variant of principal component analysis and is able to reveal systematic variation signatures existing on a die-to-die and wafer-to-wafer scale individually. Separation of die variation from wafer variation facilitates understanding of a nature and source of the process uncertainty. Experimental results show that the most dominant die-to-die variation and wafer-to-wafer variation represent 31% and 25% of the total variance of a large set of manufacturing in-line parameters in 65nm SOI CMOS technology. The process variation in RF circuit performance is also analyzed and shown to contain 66% of process variations found with manufacturing in-line parameters.