Proceedings of the Workshop on Memory Performance Issues (WMPI) during IEEE Int'l Symposium on High-Performance Computer Architectures (HPCA), Austin, Texas, February 2006.
This paper presents a comprehensive characterization study on the exploitable memory value reuse present in programs. We compare three reuse schemes: store value reuse, loaded value reuse, and macro data reuse. Macro data reuse, enabled by macro data loads, capitalizes on under-utilized cache port bandwidth and makes use of the spatial locality found in port-wide macro data. Using a generalized memory value reuse table (MVRT) model, we present the results of (1) per program reuse analysis, (2) per data size analysis, (3) per region analysis, (4) per MVRT size analysis, and (4) estimating the impact of ISA and machine widths. The macro data load mechanism is shown to open up significantly more loaded value reuse instances compared with previous loaded value reuse proposals: over 75% (SPEC2k integer), 23% (SPEC2k floating-point), and 139% (MiBench) more load-to-load forwarding opportunities using a 64-entry MVRT. We also perform a quantitative study using a realistic processor model and show that over 35% of L1 cache accesses in the SPEC2k integer and MiBench programs can be eliminated, resulting in a related energy reduction of 27% and 31% on average, respectively.