Proceedings of the IEEE Int'l Symposium on High-Performance Computer Architecture (HPCA), pp. XXX~XXX, Orlando, FL, February 2014.
Maintaining coherence in large-scale chip multiprocessors (CMPs) embodies tremendous design trade-offs in meeting the area, energy and performance requirements. Spare directory organizations represent yet the most energy-efficient and scalable approach towards many-core coherence. However, their limited associativity disallows the one-to-one correspondence of directory entries to cached blocks, rendering them inadequate in tracking all cached blocks. Unless the directory storage is generously over-provisioned, conflicts will force frequent invalidations of cached blocks, severely jeopardizing the system performance. As the chip area and power become increasingly previous with the growing core count, the storage over-provisioning approach becomes unsustainably costly. Stash Directory is a novel sparse directory design that allows directory entries tracking private blocks to be safely evicted without invalidating the corresponding cached blocks. By doing so, it improves system performance and increases the effective directory capacity, enabling significantly smaller directory designs. to ensure that coherence is correctly maintained under the new relaxed inclusion property, some minimum responsibility is delegated to the last level cache and the coherence protocol without however raising overhead concerns. Simulations on a 16-core CMP model shows that Stash Directory can reduce space requirements to 1/8 of a conventional sparse directory, without compromising performance.