Proceedings of the 2nd IEEE Asia Pacific Conference on ASICs (AP-ASIC), pp. 285~289, Cheju, Korea, August 2000.
Architecting today's embedded processor core faces several important design challenges: low power, high performance, and system-on-a-chip considerations. Moreover, support for high-level language constructs and operating systems becomes increasingly critical for acceptance to various applications. CalmRISCTM-32 effectively meets these challenges by incorporating a carefully designed instruction set, an energy-efficient pipeline design, debugging support with trace mode/CalmBreakerTM (an in-circuit debugger), and a generic, yet efficient coprocessor interface. Using a 0.25um static CMOS standard cell library and compiled datapath cells, the first implementation of CalmRISCTM-32 operates at 130MHz (under worst conditions) and consumes 150mA/MHz at 2.5V. This paper presents a brief description of the instruction set, the overall microarchitecture, and the coprocessor interface of CalmRISCTM-32.